Verilog case vs casex

I will consider this as a option at 4x compiled versions. Generally speaking, it is likely that compilation is getting slower when veritak is updated.

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Yes, though it is very primitive and interim. By seeing the same waveform view between us, I think I can understand what is the problem clearly.

Commenting out the always GSR and the initial blocks makes no difference. It's fun for mixed analog engineer. I've investigated this issue, however I can not solve the issue so far.

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